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Trace-Based Post-Silicon Validation for VLSI Circuits

LNEE: TRACE-BASED POST-SILICON VALIDTION FOR VLSI CRCTS

Engineering

Mathematics & Science

Gt Product Group

Binding Format

Marketing Imprint Name

B2B GT

CL Carton Count

Imprint Name

B2B & B2C

This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuits, and ultimately enable the design and fabrication of reliable electronic devices.

POST SECONDARY FOUR YEAR

COLFR

COLJR

COLSO

COLSR

Duration

Duration Unit Of Measure

Transaction Type

Front Cover.
Half Title Page.
Title Page.
Copyright Page.
Dedication.
Preface.
Acknowledgments.
Contents.
1: Introduction.
2: State of the Art on Post-Silicon Validation.
3: Signal Selection for Visibility Enhancement.
4: Multiplexed Tracing for Design Error.
5: Tracing for Electrical Error.
6: Reusing Test Access Mechanisms.
7: Interconnection Fabric for Flexible Tracing.
8: Interconnection Fabric for Systematic Tracing.
9: Conclusion.
References.
Index.

Trace-Based Post-Silicon Validation for VLSI Circuits.css-1p8rvzy{position:absolute;padding-left:8px;}

Trace-Based Post-Silicon Validation for VLSI Circuits