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Pipelined Multiprocessor System-on-Chip for Multimedia

PIPELINED MULTIPROCESSOR SYSTEM ON CHIP FOR MULTIMEDIA

Engineering

Mathematics & Science

Gt Product Group

Binding Format

Marketing Imprint Name

B2B GT

CL Carton Count

Imprint Name

B2B & B2C

This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint. A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors' combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.

POST SECONDARY FOUR YEAR

COLFR

COLSO

COLJR

COLSR

Duration

Duration Unit Of Measure

Transaction Type

Front Cover.
Half Title Page.
Title Page.
Copyright Page.
Contents.
1: Introduction.
2: Literature Survey.
3: Optimisation Framework.
4: Performance Estimation of Pipelined MPSoCs.
5: Design Space Exploration of Pipelined MPSoCs.
6: Adaptive Pipelined Mpsocs.
7: Power Management in Adaptive Pipelined MPSoCs.
8: Multi-Mode Pipelined MPSoCs.
9: Conclusions and Future Work.
Index.

Pipelined Multiprocessor System-on-Chip for Multimedia.css-1p8rvzy{position:absolute;padding-left:8px;}

Pipelined Multiprocessor System-on-Chip for Multimedia