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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

DSGN-FOR-TEST TEST OPTMZTN TECHQS TSV-BASD 3D STCKD ICS

Physics

Mathematics & Science

Gt Product Group

Binding Format

Marketing Imprint Name

B2B GT

CL Carton Count

Imprint Name

B2B & B2C

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

POST SECONDARY FOUR YEAR

PROFESSIONAL & REFERENCE

COLFR

COLSO

COLJR

COLSR

Duration

Duration Unit Of Measure

Transaction Type

Front Cover.
Half Title Page.
Title Page.
Copyright Page.
Dedication.
Foreword.
Preface.
Acknowledgements.
Contents.
1: Introduction.
2: Wafer Stacking and 3D Memory Test.
3: Built-In Self-Test for TSVs.
4: Pre-Bond TSV Test through TSV Probing.
5: Pre-Bond Scan Test through TSV Probing.
6: Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths.
7: Post-Bond Test Wrappers and Emerging Test Standards.
8: Test-Architecture Optimization and Test Scheduling.
9: Conclusions.
References.

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs.css-1p8rvzy{position:absolute;padding-left:8px;}

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs