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Models, Methods, and Tools for Complex Chip Design

LNEE: MODELS METHODS AND TOOLS FOR COMPLEX CHIP DESIGN

Engineering

Mathematics & Science

Gt Product Group

Binding Format

Marketing Imprint Name

B2B GT

CL Carton Count

Imprint Name

B2B & B2C

This book brings together a selection of the best papers from the fifteenth edition of the Forum on specification and Design Languages Conference (FDL), which was held in September 2012 at Vienna University of Technology, Vienna, Austria. FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems.

POST SECONDARY FOUR YEAR

COLFR

COLJR

COLSO

COLSR

Duration

Duration Unit Of Measure

Transaction Type

Front Cover.
Half Title Page.
Title Page.
Copyright Page.
Preface.
Contents.
Contributors.
1: Formal Plausibility Checks for Environment Constraints.
2: Efficient Refinement Strategy Exploiting Component Properties in a CEGAR Process.
3: Formal Specification Level.
4: TLM POWER3: Power Estimation Methodology for SystemC TLM 2.0.
5: SCandal: SystemC Analysis for Nondeterminism Anomalies.
6: A Design and Verification Methodology for Mixed-Signal Systems Using SystemC-AMS.
7: Configurable Load Emulation Using FPGA and Power Amplifiers for Automotive Power ICs.
8: Model Based Design of Distributed Embedded Cyber Physical Systems.
9: Model-Driven Methodology for the Development of Multi-level Executable Environments.
10: GREEN HOME: The Concept and Study of Grid Responsiveness.
11: Polynomial Metamodel-Based Fast Optimization of Nanoscale PLL Components.
12: Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures.

Models, Methods, and Tools for Complex Chip Design.css-1p8rvzy{position:absolute;padding-left:8px;}

Models, Methods, and Tools for Complex Chip Design