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Finite State Machine Logic Synthesis for Complex Programmable Logic Devices

LNEE: FINITE ST MCHN LGC SYNTHSS CMPLX PRGRMMBL LGC DEV

Engineering

Mathematics & Science

Gt Product Group

Binding Format

Marketing Imprint Name

B2B GT

CL Carton Count

Imprint Name

B2B & B2C

This book is a monograph devoted to logic synthesis and optimization for CPLDs. CPLDs' macrocell can also be interpreted as programmable AND-fixed OR structure, well known as PAL-based structure. The question is: what should be done when the number of implicants representing function exceeds the number of product terms available in a logic block. The answer is ... in the book.Logic synthesis and optimization methods dedicated for PAL-based structures are proposed. The methods strive to find the optimum fit for the combinational logic and finite state machines to the structure of the logic device and aim at area and speed optimization. The theoretical background and complete strategies are richly illustrated with examples and figures.

POST SECONDARY FOUR YEAR

COLFR

COLSO

COLJR

COLSR

Duration

Duration Unit Of Measure

Transaction Type

Front Cover.
Other Frontmatter.
Title Page.
Copyright Page.
Dedication.
Preface.
Contents.
Symbols.
Acronyms.
1: Introduction.
2: Definitions and Basic Properties.
3: Synthesis of FSMs.
4: State Assignment Algorithms.
5: Area Optimization Based on Graphs of Outputs.
6: Speed Optimization Using Tri-State Output Buffers.
7: Complex Strategies for FSMs.
8: Experiments.
9: Conclusions.
Appendix A: File Formats.
Appendix B: ESPRESSO Minimizer.
Index.

Finite State Machine Logic Synthesis for Complex Programmable Logic Devices.css-1p8rvzy{position:absolute;padding-left:8px;}

Finite State Machine Logic Synthesis for Complex Programmable Logic Devices