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Protecting Chips Against Hold Time Violations Due to Variability

PRTCTNG CHIPS AGNST HLD TME VIOLATNS DUE TO VARIABILITY

Engineering

Mathematics & Science

Gt Product Group

Binding Format

Marketing Imprint Name

B2B GT

CL Carton Count

Imprint Name

B2B & B2C

With the development of Very-Deep Sub-Micron technologies, process variability is becoming increasingly important and is a very important issue in the design of complex circuits. Process variability is the statistical variation of process parameters, meaning that these parameters do not have always the same value, but become a random variable, with a given mean value and standard deviation. This effect can lead to several issues in digital circuit design.The logical consequence of this parameter variation is that circuit characteristics, as delay and power, also become random variables. Because of the delay variability, not all circuits will now have the same performance, but some will be faster and some slower. However, the slowest circuits may be so slow that they will not be appropriate for sale. On the other hand, the fastest circuits that could be sold for a higher price can be very leaky, and also not very appropriate for sale. A main consequence of power variability is that the power consumption of some circuits will be different than expected, reducing reliability, average life expectancy and warranty of products. Sometimes the circuits will not work at all, due to reasons associated with process variations. At the end, these effects result in lower yield and lower profitability.To understand these effects, it is necessary to study the consequences of variability in several aspects of circuit design, like logic gates, storage elements, clock distribution, and any other that can be affected by process variations. The main focus of this book will be storage elements.

POST SECONDARY FOUR YEAR

COLFR

COLJR

COLSO

COLSR

Duration

Duration Unit Of Measure

Transaction Type

Front Cover.
Half Title Page.
Title Page.
Copyright Page.
Dedication.
Contents.
About the Authors.
1: Introduction: Process Variations and Flip-Flops.
2: Process Variability: Overview.
3: Flip-Flops and Hold Time Violations: Definitions.
4: Circuits under Test: For Characterization.
5: Measurement Circuits: For Precise Characterization.
6: Experimental Results: Of Fabricated Circuits.
7: Systematic and Random Variability: Of Measured Results.
8: Normality Tests: Of Measured Results.
9: Probability of Hold Time Violations: Of Short Logic Paths.
10: Protecting Circuits against Hold Time Violations: Due to Process Variability.
11: Padding Efficiency: Of the Proposed Padding Algorithm.
12: Final Remarks.
References.

Protecting Chips Against Hold Time Violations Due to Variability.css-1p8rvzy{position:absolute;padding-left:8px;}

Protecting Chips Against Hold Time Violations Due to Variability